International Research Journal of Innovations in Engineering and Technology - IRJIET International Open Access, Monthly, Peer Reviewed, Reputed Journal ISSN (online): 2581-3048

ESTD Year: 2017 | Impact Factor: 6.9

DOI Prefix: 10.47001/IRJIET

Design and Pre-Layout Simulation of a 6-bit CMOS Pipeline ADC

Kuldeep SinghDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, IndiaPiyush KumarDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, IndiaAnkurDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, IndiaSheetalDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, IndiaBhaviDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, IndiaVinod KumarDepartment of Electrical and Electronics Engineering, Guru Jambheshwar University of Science and Technology, Hisar, Haryana, India

Vol 10 No 9 (2026): Volume 10, Issue 9, September 2026 | Pages: 62-69

International Research Journal of Innovations in Engineering and Technology

OPEN ACCESS | Research Article | Published Date: 17-09-2026

doi Logo doi.org/10.47001/IRJIET/2026.109007

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Abstract

This paper presents a circuit schematic level design and functional simulation of six stage, 1 bit per stage CMOS Pipeline analog to digital converter (ADC) in Cadence Virtuoso. Each stage comprises sampling, binary threshold comparison, reference selection, subtraction and nominal gain of two residue amplification. The ideal stage transfer is derived and used to clarify bit significance, code formation, and pipeline timing delay. AC, DC, and Transient simulation of schematics of operational amplifier, sample and hold circuit, comparator, residue path and cascaded stage responses. The analyzed waveforms demonstrate block level operation and stage wise bit generation at a sampling rate of 10kS/s.

Keywords

Analog to digital converter, Cadence virtuoso, C-MOS analog circuit, pipeline ADC, residue amplifier, sample-and-hold circuit


Citation of this Article

Kuldeep Singh, Piyush Kumar, Ankur, Sheetal, Bhavi, & Vinod Kumar. (2026). Design and Pre-Layout Simulation of a 6-bit CMOS Pipeline ADC. International Research Journal of Innovations in Engineering and Technology - IRJIET, 10(9), 62-69. Article DOI https://doi.org/10.47001/IRJIET/2026.109007

Licence Copyright (c) 2026 International Research Journal of Innovations in Engineering and Technology creative common licence This work is licensed under Creative common Attribution Non Commercial 4.0 Internation Licence
References
  1. W. Kester, Ed., The Data Conversion Handbook. Burlington, MA, USA: Elsevier, Newnes, 2005.
  2. S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954–961, Dec. 1987, doi: 10.1109/JSSC.1987.1052843.
  3. S.-H. Lee and B.-S. Song, “Digital-domain calibration of multistep analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1679–1688, Dec. 1992, doi: 10.1109/4.173093.
  4. M. Gustavsson, J. J. Wikner, and N. N. Tan, CMOS Data Converters for Communications. Boston, MA, USA: Kluwer Academic Publishers, 2000.
  5. B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916–1926, Dec. 1992, doi: 10.1109/4.173122.
  6. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA: McGraw-Hill, 2017.
  7. T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. Hoboken, NJ, USA: Wiley, 2012.
  8. F. Maloberti, Data Converters. Dordrecht, The Netherlands: Springer, 2007.
  9. IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2010, Jan. 2011.
  10. S. H. Lewis, H. S. Fetterman, G. F. Gross, R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, Mar. 1992, doi: 10.1109/4.121557.
  11. S. H. Lewis, “Optimizing the stage resolution in pipelined, multistage analog-to-digital converters for video-rate applications,” IEEE Trans. Circuits Syst. II, vol. 39, no. 8, pp. 516–523, Aug. 1992, doi: 10.1109/82.168943.
  12. T. B. Cho and P. R. Gray, “A 10-b, 20-Msample/s, 35-mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar. 1995, doi: 10.1109/4.364429.
  13. A.N. Karanicolas, H.-S. Lee, and K. L. Bacrania, “A 15-b 1-Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207–1215, Dec. 1993, doi: 10.1109/4.261994.
  14. I.Ahmed, Pipelined ADC Design and Enhancement Techniques. Dordrecht, The Netherlands: Springer, 2010, doi: 10.1007/978-90-481-8652-5.
  15. B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003, doi: 10.1109/JSSC.2003.819167.
  16. E. Iroaga and B. Murmann, “A 12-bit 75-MS/s pipelined ADC using incomplete settling,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 748–756, Apr. 2007, doi: 10.1109/JSSC.2007.892154.
  17. I.Ahmed and D. A. Johns, “An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage,” IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1626–1637, July 2008, doi: 10.1109/JSSC.2008.923724.
  18. I.Ahmed and D. A. Johns, “A high bandwidth power scalable sub-sampling 10-bit pipelined ADC with embedded sample and hold,” IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1638–1647, July 2008, doi: 10.1109/JSSC.2008.923727.

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